Flip-Flop and Latch Types.ĭesigned for advanced undergraduate and graduate computer science, computer engineering and electrical engineering courses in digital design and hardware description languages, this textbook presents an integrated treatment of the Verilog hardware description language (HDL) and its use in VLSI, circuit modeling/design, synthesis, and rapid prototyping. Backus-Naur (BNF) Formal Syntax Notation. Rapid Prototyping with Verilog and FPGAs. FIFO Application: Temperature Monitor System. Combination and Resolution of Signal Strengths. Switch-Level Models of Static CMOS Circuits. Synthesis of case and Conditional (if.) Statements. Restrictions on Synthesis of "x" and "z". Design Partitions and Hierarchical Structures. Styles for Synthesis of Combinational Logic. Behavioral Models of Finite State Machines. Simulation of Simultaneous Procedural Assignment. Intra-Assignment Delay-Non-Blocking Assignment. Intra-Assignment Delay-Blocked Assignments. Procedural Timing Controls and Synchronization. Inertial Delay Effects and Pulse Rejection. Verilog Models for Net Delay (Transport Delay). Verilog Models for Gate Propagation Delay (Inertial Delay). Logic System, Data Types, and Operators for Modeling in Verilog HDL. Structured (Top-Down) Design Methodology. Hardware Encapsulation: the Verilog Module.The Role and Requirements of HDLs in EDA. Introduction to Electronic Design Automation.
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